(1) Field of the Invention
The present invention relates to a termination circuit for the word lines of a semiconductor memory device, more particularly to a termination circuit which can reduce both the rise time and the fall time for a word selection signal applied to the word lines.
(2) Description of the Prior Art
In general, it is necessary to decrease both the power consumption of each memory cell and the size of each memory cell in order to increase the capacity of a semiconductor memory device. One of the methods for decreasing the power consumption of each of the memory cells is to increase the resistance value of the load resistors of each of the memory cells so that the holding current passing through non-selected word lines is decreased. However, increasing the resistance value of the load resistors leads to an increase in the transition time from a selected condition to a non-selected condition, because the fall time of the word selection signal is increased. Consequently, the desired high speed operation of the memory device can not be attained.
In order to decrease the fall time of the word selection signal applied to a word line, a conventional memory device, as disclosed in the thesis "AN ECL 100 K Compatible 1024.times.4b RAM with 15 ns Access Time", by Ulf Buerker, et al. , ISSCC DIGEST OF TECHNICAL PAPERS, Feb. 15, 1979, p. 102, includes a termination circuit as illustrated in FIG. 1.
In FIG. 1, a memory cell array MCA composed of a plurality of memory cells MC.sub.ij (i=1,2, . . . , n; j=1,2, . . . , m) whose matrix is n rows by m columns is illustrated. Each of the memory cells MC.sub.ij is a well known flip-flop type cell. The memory cell, for example MC.sub.11, includes two multiemitter transistors T.sub.1 and T.sub.2, two load resisters R.sub.1 and R.sub.2, and two diodes D.sub.1 and D.sub.2, which are connected parallel to the load resisters R.sub.1 and R.sub.2, respectively. One of the emitter electrodes of the multiemitter transistor T.sub.1 is connected to a hold line HL.sub.1 and the other emitter electode of the multiemitter transistor T.sub.1 is connected to a bit line B.sub.1. One of the emitter electrodes of the multiemitter transistor T.sub.2 is connected to the hold line HL.sub.1 and the other emitter electrode of the multiemitter transistor T.sub.2 is connected to a bit line B.sub.1. The word lines WL.sub.1, WL.sub.2, . . . , WL.sub.n are connected to word line drivers WD.sub.1, WD.sub.2, . . . , WD.sub.n respectively. The hold lines HL.sub.1, HL.sub.2. . . , HL.sub.n are connected to hold current sources 1.sub.1, 1.sub.2, . . . , 1.sub.n respectively. The hole lines HL.sub.1, HL.sub.2, . . . , HL.sub.n are also connected to the anode electrode of diodes D.sub.11, D.sub.12, . . . , D.sub.1n, respectively, of a termination circuit 1, and the cathode electrodes of the diodes D.sub.11, D.sub.12, . . . , D.sub.1n are commonly connected to an additional current source 10.
One of the memory cells MC.sub.ij, for example the memory cell MC.sub.11, is selected by applying a high potential word selection signal to the word driver WD.sub.1 and a high potential bit selection signal to a bit line driver connected to the bit line pair B.sub.1 and B.sub.1, not shown in FIG. 1. Therefore, the potential of the selected word line is high and the potentials of the non-selected word lines are low. The potential of the hold line is lower than the corresponding word line by a nearly constant value, i.e., the base-emitter voltage of one of the transistors in the memory cell.
The termination circuit 1 of the memory device of FIG. 1 helps to reduce the fall time of the potential of the word line, for example WL.sub.1, whenever the word line changes its state from the selected condition to the non-selected condition, by adding the current .DELTA.I.sub.H to the current I.sub.H flowing from the selected word line WL.sub.1 through the memory cells MC.sub.11, . . . , MC.sub.1m to the hold line HL.sub.1. Since the potential level of the hold line HL.sub.1, corresponding to the selected word line WL.sub.1, is higher than that of the other hold lines HL.sub.2, . . . , HL.sub.n, the diode D.sub.11 connected to the selected hold line HL.sub.1 is turned on and the current .DELTA.I.sub.H flows from the selected hold line HL.sub.1 through the diode D.sub.11 to the additional current source 10. Consequently, the potential level of the hold line HL.sub.1 and, thus the potential level of the word line WL.sub.1 falls quickly. The additional current .DELTA.I.sub.H serves to quickly discharge the electric charge stored in the stray capacitance included in the word line, the hold line and the memory cells connected between the word line and the hold line, so that the potential drop of the word line is accelerated.
In order to decrease the operation time of a memory device, for example, the read out time, it is necessary to quickly lower the output potential of a non-selected memory cell. This quick reduction of the output potential of a non-selected memory cell is necessary because a read out current flows from the non-selected memory cell to the bit line even when the potential level of the non-selected memory cell is high, and a read out from the next selected memory cell cannot begin before the potential level of the non-selected memory cell drops. The potential level of the non-selected memory cell does not fall quickly, even if the potential level of the word line falls quickly, because of stray capacitance contained in the memory cell. Therefore, as mentioned above, the potential of the memory cell is forced to drop to a low level by the additional current .DELTA.I.sub.H flowing from the memory cell through the hold line to the additional current source 10. It should be noted that the additional current flow is required temporarily during the transition period from the selected condition to the non-selected condition.
FIG. 2 illustrates graphically the relationship between the potential of two word lines, one which is, for example, the word line WL.sub.1 which had been previously selected and which is changing its potential from high (selected condition) to low (non-selected condition); and the other word line which is, for example, the word line WL.sub.2 which was selected after the word line WL.sub.1 and which is changing its potential from low to high. The dotted lines in FIG. 2 illustrate the characteristics of the potential of the two word lines WL.sub.1 and WL.sub.2 when the termination circuit 1 of FIG. 1 is not used, and the solid lines illustrate the potential of the two word lines WL.sub.1 and WL.sub.2 when the termination circuit of FIG. 1 is used. As shown in FIG. 2, a cross point CP of the solid lines comes faster than a cross point CP' of the dotted lines because of the termination circuit 1.
Although the termination circuit 1 can reduce the fall time of the potential of the word line, for example, WL.sub.1 until the cross point CP is reached, the fall time after the cross point CP cannot be reduced. The further reduction cannot be accomplished because the additional current .DELTA.I.sub.H does not flow from the hold line HL.sub.1 but flows from the hold line HL.sub.2 to the additional current source 10 after the cross point CP has been reached. That is, among the diodes D.sub.11, D.sub.12, . . . , D.sub.1n of the termination circuit 1, only the diode which is connected to the hold line having the highest potential turns on. Until the cross point CP is reached the diode D.sub.11 is turned on and after the cross point CP is reached the diode D.sub.12 is turned on. Therefore, until the cross point CP is reached, the additional current .DELTA.I.sub.H flows from the hold line HL.sub.1, corresponding to the word line WL.sub.1 which had been previously selected; and after the cross point CP, the additional current .DELTA.I.sub.H flows from the hold line HL.sub.2, corresponding to the word line WL.sub.2 which was selected subsequent to the word line WL.sub.1, so that only the hold current I.sub.H flows through the hold line HL.sub.1.
FIG. 3 illustrates other conventional termination circuits 2.sub.1, 2.sub.2, . . . , 2.sub.n, as disclosed in the thesis "A 6 ns 4 Kb Bipolar RAM using Switched Load Resistor Memory Cell", by Masaaki Inadachi, et al., ISSCC DIGEST OF TECHNICAL PAPERS, Feb. 15, 1979, p. 108. The termination circuit, for example, 2.sub.1 reduces the fall time for the potential level of the word line WL.sub.1 by delaying the trailing edge of the word selection signal on the word line WL.sub.1 and not delaying the leading edge of the word selection signal on the word line WL.sub.2, so that the additional current .DELTA.I.sub.H flows from the hold line HL.sub.1, corresponding to the word line WL.sub.1, to the current source .DELTA.I.sub.H until the potential level of the word line WL.sub.1 falls to a substantially low level, even after the word line WL.sub.1 has changed its state from the selected condition to the non-selected condition.
One of the termination circuits 2.sub.1, 2.sub.2, . . . , 2.sub.n of FIG. 3, for example, the termination circuit 2.sub.1, includes an NPN type transistor T.sub.31. The collector electrode of transistor T.sub.31 is connected to the word line WL.sub.1 through a resistor R.sub.31 and a capacitor C.sub.31 connected in parallel and, the emitter electrode is connected to a negative voltage source line NL through a resistor R.sub.33 and the base electrode is connected to a reference voltage source V.sub.REF having a constant voltage, causing the transistor T.sub.31 to operate as a constant current source. The termination circuit 2.sub.1 also includes an NPN type transistor T.sub.32, the base electrode of transistor T.sub.32 is connected to the collector electrode (point A) of the transistor T.sub.31, the collector electrode is connected to the ground and the emitter electrode is connected to the negative voltage source line NL through a resistor R.sub.32 and a capacitor C.sub.32 connected in parallel. The termination circuit 2.sub.1 further includes an NPN type transistor T.sub.33, the base electrode of transistor T.sub.33 is connected to the emitter electrode (point B) of the transistor T.sub.32, the collector electrode of transistor T.sub.33 is connected to the hold line HL.sub.1 and the emitter electrode is connected to the negative voltage source line NL through a resistor R.sub.34.
In the termination circuit 2.sub.1 of FIG. 3, the potential of point A rises substantially at the same time as the potential rise of the word line WL.sub.1, due to the action of the capacitor C.sub.31, and the potential of the point B, which is lower than that of point A by the base-emitter voltage V.sub.BE of the transistor T.sub.32, also rises at substantially the same time as the potential rise of the word line WL.sub.1. Therefore, transistor T.sub.33 turns on immediately after the potential rise of the selected word line WL.sub.1, and the additional current .DELTA.I.sub.H flows from the hold line HL.sub.1 through the transistor T.sub.33 and the resistor R.sub.34 to the negative voltage source line NL. When the potential of the word line WL.sub.1 drops, due to the transition from the selected condition to the non-selected condition, the potential of the point B does not fall immediately but falls slowly, due to the action of the capacitor C.sub.32, so that the transistor T.sub.33 does not turn off immediately after the drop of the potential of the word line WL.sub.1 but continues in a turned on condition for a short time. Therefore, as shown in FIG. 4, the additional current .DELTA.I.sub.H continues to flow through the hold line HL.sub.1 for a predetermined time period .DELTA.t, even after the potential V.sub.W of the word line WL.sub.1 has fallen from the high level (selected condition) to the low level (non-selected condition). Consequently, the fall time for the potential V.sub.W of the word line is reduced as shown by a solid line in FIG. 4. In FIG. 4, dotted lines show the characteristics of the potential V.sub.W of the word line and the additional current .DELTA.I.sub.H of the circuit of FIG. 1.
However, in the termination circuit 2.sub.1 of FIG. 3, the transistor T.sub.33 turns on immediately after the potential rise of the word line WL.sub.1 and the additional current .DELTA.I.sub.H flows immediately through the hold line HL.sub.1, corresponding to the word line WL.sub.1. Therefore, the load of the word line WL.sub.1, i.e., the load on the word line driver WD.sub.1, becomes heavy during the potential rise of the word line WL.sub.1, causing the rise time for the potential V.sub.W of the word line WL.sub.1 to be increased when the word line driver WD.sub.1 does not have a large driving capability.
The termination circuits 2.sub.1, 2.sub.2, . . . , 2.sub.n of FIG. 3 also have the disadvantage that each of the termination circuits 2.sub.1, 2.sub.2, . . . , 2.sub.n of FIG. 3 uses many circuit parts, including two capacitors, for example, C.sub.31 and C.sub.32, so that the area occupied by each of the termination circuits 2.sub.1, 2.sub.2, . . . , 2.sub.n in an integrated circuit of a memory device becomes large. Another disadvantage is that a termination circuit 2.sub.1, 2.sub.2, . . . , 2.sub.n-1 or 2.sub.n is provided for each of the word lines of a memory device, and therefore, a memory device of, for example, 4 Kbits (64.times.64 bits), which has 64 word lines, needs 64 termination circuits, thus requiring a large area for the termination circuits.